The present invention relates generally to the manufacturing of multi-layer ceramic integrated circuit packages for the electronics industry, and is particularly concerned with the stage in manufacturing at which holes are formed in a predetermined pattern in ceramic layers and filled with ink.
Integrated circuit packages are made from several flat layers of ceramic. Conductive paths are provided between successive layers by means of aligned holes, known as via holes, which are filled with conductive ink or paste.
The packages are fabricated by first punching the desired hole pattern into a flat ceramic wafer, and subsequently filling the punched holes with conductive ink. The desired conductor pattern is then screen printed onto the surface of the wafer. The multiple layers that make up the package are then stacked together and laminated together under high pressure to produce a composite laminated structure.
Currently, various techniques are used to fill the formed via holes. In one example, a mask having holes corresponding to those in the wafer is placed over the wafer with the holes in alignment. Ink is then spread over the mask with a squeegee device which presses ink through the mask into the wafer. This technique can cause some spreading of ink around the via holes.
Another method for filing via holes is described in U.S. Pat. No. 4,519,760 of Norell. In this method, a wafer having pre-formed holes is placed on a base. A hollow member having an open face covered by a mask with holes corresponding to those in the wafer is placed over the base. A diaphragm filled with conductive ink is located in the hollow member, and pressure is applied to the diaphragm to force ink out through the mask holes and into the holes of the wafer. One problem with this is that the holes in the mask must be properly aligned with the holes in the wafer for complete filling to occur.